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HANBit
HMD1M32M2GL
4Mbyte(1Mx32) Fast Page Mode, 1K Refresh, 72Pin SIMM, 5V Design Part No. HMD1M32M2GL
DESCRIPTION
The HMD1M32M2GL is an 1M x 32 bits Dynamic RAM MODULE which is assembled 2 pieces of 1M x 16bit DRAMs in 42 pin SOJ package on single sides the printed circuit board with decoupling capacitors. The HMD1M32M2GL is optimized for application to the systems, which are required high density and large capacity such as main memory of the computers and an image memory systems, and to the others, which are, requested compact size. The HMD1M32M2GL provides common data and outputs.
Features PIN ASSIGNMENT
w 72 pins Single In-Line Package w Fast Page Mode Capability w Single +5V 0.5V power supply w Fast Access Time & Cycle Time tRAC HMD1M32M2G-5 HMD1M32M2G-6 w Low Power w /RAS Only Refresh, /CAS before /RAS Refresh, Hidden Refresh Capability w All inputs and outputs TTL Compatible w 1,024 Refresh Cycles/16ms 50 60 tCAC 15 15 tRC 90 110 tPC 35 40 PIN 1 2 3 4 5 6 7 8 9 10 11 12 SYMBOL Vss DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc /WEO A0 A1 A2 A3 A4 A5 A6 A7 DQ4 DQ20 DQ5 DQ21 DQ6 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBO L DQ22 DQ7 DQ23 A8 NC(A10) Vcc /WE2 NC Vcc /RAS Vcc NC NC /OE Vss /CAS Vcc NC NC NC A9 NC(A11) /WE1 Vcc PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 /WE3 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 Vcc NC NC Vss NC Vss Vss
PIN DESCRIPTION
PIN A0 - A9 DQ0 - DQ31 /RAS /CAS /OE FUNCTION Address Inputs Data Input/Output Row Address Strobe Column Address Strobe Data Output Enable PIN /WE Vcc Vss NC FUNCTION Read/Write Enable Power (+5V) Ground No Connection
13 14 15 16 17 18 19 20 21 22 23 24
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FUNCTIONAL BLOCK DIAGRAM U1
/RAS /CAS0 /LCAS /CAS1 /UCAS /RAS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
HMD1M32M2GL
DQ0-DQ7
/OE
/OE /WE A0-A9
DQ8-DQ15
/RAS /RAS /LCAS /CAS2 /UCAS /CAS3
U2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9D Q10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ16-DQ23
/OE
DQ24-DQ31
/WE /WE A0-A9
A0-A9
Vcc Vss
0.1uF Capacitor
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ABSOLUTE MAXIMUM RATINGS*
SYMBOL TA TSTG VIN/VOUT VCC IOUT PD PARAMETER Ambient Temperature under Bias Storage Temperature (Plastic) Voltage on any Pin Relative to Vss Power Supply Voltage Short Circuit Output Current Power Dissipation RATING 0 ~ 70 -55 ~ 150 -1.0 ~ 7.0 -1.0 ~ 7.0 100 2
HMD1M32M2GL
UNIT C C V V mA W
*NOTE: 1. Stress greater than above absolute Maximum Ratings?
May cause permanent damage to the device.
RECOMMENDED DC OPERATING CONDITIONS (TA = 0 ~ 70C)
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage *NOTE: All voltages referenced to Vcc SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL VOH VOL ICC1 (/RAS,/CAS,Address Cycling : tRC = tRC min) ICC2 ICC3 (/RAS Cycling, /CAS = VIH,: tRC = tRC min) Fast Page Mode Current ICC4 (/RAS =VIL, /CAS, Address Cycling : tPC = tPC min) ICC5 ICC6 Standby Current (/RAS,/CAS >= Vcc - 0.2V) -5 /CAS before /RAS Refresh Current (tRC = tRC min) -6 Self Refresh Current ICCS (/RAS=/UCAS=/LCAS=VIL, /WE=/OE=A0~A9= Vcc - 0.2V or 0.2V, DQ0~DQ31= Vcc - 0.2V, 0.2V or Open) Input Leakage Current II(L) IO(L) -10 (Any Input (0V<=VIN<= VIN + 0.5V, All Other Pins Not Under Test = 0V) Output Leakage Current(DOUT is Disabled, 0V<=V OUT<= Vcc) -10 10 uA 10 uA 400 uA 260 mA -6 160 2 280 mA mA -6 -5 260 180 mA Standby Current (/RAS,/CAS = VIH) /RAS Only Refresh Current -5 -6 260 4 280 mA mA PARAMETER Output High Level Voltage (IOUT = -5mA) Output Low Level Voltage (IOUT = 4.2mA) Operating Current -5 MIN 2.4 0 0.4 280 mA MAX UNIT V V
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Note: 1. Icc depends on output load condition when the device is selected. Icc (max) is specified at the output open condition. 2. Address can be changed once or less while /RAS = V IL. 3. Address can be changed once or less while /CAS = V IH
HMD1M32M2GL
CAPACITANCE
( TA=25 C, Vcc = 5V+/- 10%, f = 1Mhz ) SYMBOL CI1 C I2 MIN MAX 5 7 UNITS pF pF NOTE 1 1,2
o
DESCRIPTION Input Capacitance (A0-A9) Input Capacitance (/WE,/RAS, /CAS0/CAS3,/OE) Input/Output Capacitance (DQ0-31)
CDQ1
-
7
pF
1,2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /CAS = VIH to disable DOUT.
AC CHARACTERISTICS ( 0
SYMBOL tRC tRWC tRAC tCAC Taa tOFF tT TRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH
o
C TA 70oC , Vcc = 5V10%, VIH /VIL = 2.4/0.8V, VOH /VOL =2.4/0.4V, See notes 1,2) -5 -6 UNIT MIN MAX MIN 110 155 50 15 25 0 3 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 10K 37 25 10K 13 50 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 10K 45 30 10K 60 15 30 15 50 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 11 11 4 10 3,4,10 3,4,5 3,10 6 2 90 133 NOTE
PARAMETER Random Read or Write Cycle Time Read-modify-writer cycle time Access Time from /RAS Access Time from /CAS Access Time from Column Address Output Buffer Turn-off Time Transition Time (Rise and Fall) /RAS Precharge Time /RAS Pulse Width /RAS Hold Time /CAS Hold Time /CAS Pulse Width /RAS to /CAS Delay Time /RAS to Column Address Delay Time /CAS to /RAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address to /RAS Lead Time Read Command Setup Time Read Command Hold Time to /CAS
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tRRH tWCH tWP tRWL tCWL tDS tDH tREF twcs tCWD tRWD tAWD tCPWD tCSR (/CAS-before-/RAS Refresh Cycle) /CAS Hold Time tCHR (/CAS-before-/RAS Refresh Cycle) tRPC tCPA tPC tCP tRASP tRHCP Precharge tOEA tOED tOEZ tOEH tRASS tPRS /OE Access Time /OE to data delay Output buffer turn off delay time from /OE /OE command hold time /RAS Pulse Width(CBR self refresh) /RAS Precharge Time(CBR self refresh) 13 0 13 100 90 13 13 15 0 15 100 110 /RAS Precharge to /CAS Hold Time Access Time from /CAS Precharge Fast Page Mode Cycle Time Fast Page Mode /RAS Precharge Time Fast Page Mode /CAS Pulse Time /RAS Hold Time time from /CAS 30 35 35 10 50 200K 5 30 40 10 60 5 10 10 Read Command Hold Time to /RAS Write Command Hold Time Write Command Pulse Width Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Setup Time Data-in Hold Time Refresh Period (1024 Cycle) Write Command Setup Time /CAS to /WE delay time /RAS to /WE delay time Column Address to /WE delay time /CAS precharge to /WE delay time /CAS Setup Time 5 5 0 36 73 48 53 0 10 10 13 13 0 10 16 0 40 85 55 60 0 10 10 15 15 0 10
HMD1M32M2GL
ns ns ns ns ns ns ns 16 ms ms ms ns ns ns ns 7 7,13 7 7 7 15 9 9 8
ns ns 35 ns ns ns 200K ns ns 15 ns ns 15 ns ns us ns
16
3
12
3
/CAS Hold Time(CBR self refresh) -50 -50 ns tCHS Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are VIH / VIL. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between . VIH and VIL are assumed to be 5ns for all inputs. 3. Measured with a load circuit equivalent to 2TTL loads and 100pF. 4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD <= tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH / VOL . 7. TWCS, TRWD, TCWD, TCPWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If twcs >= twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout
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HMD1M32M2GL
the entire cycle. If tCWD >= tCWD (min), tRWD >= tRWD (min), TCPWD>= TCPWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycles. 9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled write cycle and read-modify-write cycles. 10. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 11. tASC, tCAH are are referenced to the earlier /CAS falling edge. 12. tCP is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle. 13. tCWD is referenced to the later /CAS falling edge at word read-modify-write cycle. 14. tCWL is specified from /WE falling edge to the earlier /CAS rising edge . 15. tCSR is referenced to the earlier /CAS falling edge before /RAS transition low. 16. tCHR is referenced to the later /CAS rising edge after /RAS transition low.
PACKAGING INFORMATION
0.25 mm MAX
2.54 mm MIN
1.270.08 mm 1.27 mm
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ORDERING INFORMATION
Part Number Density Org. Package Component Number 2EA 2EA Vcc
HMD1M32M2GL
MODE
SPEED
HMD1M32M2GL-5 HMD1M32M2GL-6
4MByte 4MByte
X32 x 32
72 Pin-SIMM 72 Pin-SIMM
5V 5V
FP FP
50ns 60ns
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